FPGA Based Quadruple Precision Floating Point Arithmetic for Scientific Computations

In this project we explore the capability and flexibility of FPGA solutions in a sense to accelerate scientific computing applications which require very high precision arithmetic, based on IEEE 754 standard 128-bit floating-point number representations. Field Programmable Gate Arrays (FPGA) is increasingly being used to design high end computationally intense microprocessors capable of handling floating point mathematical operations. Quadruple Precision Floating-Point Arithmetic is important in computational fluid dynamics and physical modelling, which require accurate numerical computations. However, modern computers perform binary arithmetic, which has flaws in representing and rounding the numbers. As the demand for quadruple precision floating point arithmetic is predicted to grow, the IEEE 754 Standard for Floating-Point Arithmetic includes specifications for quadruple precision floating point arithmetic. We implement quadruple precision floating point arithmetic unit for all the common operations, i.e. addition, subtraction, multiplication and division. While previous work has considered circuits for low precision floatingpoint formats, we consider the implementation of 128-bit quadruple precision circuits. The project will provide arithmetic operation, simulation result, hardware design, Input via PS/2 Keyboard interface and results displayed on LCD using Xilinx virtex5 (XC5VLX110TFF1136) FPGA device.